The present invention relates to a capacitor of a semiconductor memory device, and particularly to a stacked capacitor of a DRAM and a process therefor.
The memory capacity of a semiconductor memory device, particularly of a DRAM cell, is determined by the capacity of the capacitor constituting the memory cell. Meanwhile, as the memory device gets more and more highly integrated and thus smaller in size, the area occupied by each cell is reduced, and thus the capacity of the capacitor has to suffer structural reduction. Hence, it is necessary for the capacitor to have an adequately large capacity even if the size of a memory cell gets smaller. A typical example of DRAM cell capacitors with a large capacity more than 4 mega bits is a stacked structure, wherein the storage electrodes are stacked on the substrate, so that the expanded surface areas of the storage electrodes are used to increase the capacity of the capacitor.
Referring to FIG. 1 for illustrating the cross section of a conventionally improved stacked capacitor, on the substrate 1 having an element isolating oxide layer 2, a source and a drain regions 3 and 4, a word and a bit lines 5 and 10, and an insulating layer 6 is there formed a capacitor including a fin-shaped storage electrode 7 contacting the source region 3, a dielectric layer 8 and a plate electrode 9. Over the whole surface of the substrate 1 is laid element protecting layer 11. The fin-shaped storage electrode 7 is formed by alternately depositing a plurality of polysilicon layers and a plurality of oxide layers on the substrate and etching them, and thereafter the whole substrate is immersed in an oxide etching solution to remove all the oxide layers remaining between the polysilicon layers. Then, the dielectric layer 8 and the plate electrode 9 are formed. However, in this case, the wing portions 12 and 13 of the storage electrode is susceptible to be broken when the substrate is immersed in the etching solution. Namely, if all the oxide layers between the polysilicon layers are removed, the wing portions 12 and 13 of the storage electrode 7 are suspended without any supporting layers, thus resulting in weakening of the wing portions. This drawback decreases the reliability of the process as well as causes unstable structure of a stacked capacitor formed of multiple polysilicon layers.